1. Field of the Invention
The present invention relates to a voltage-controlled oscillator (VCO), and particularly to a ring VCO that is constituted by MOS (Metal-Oxide Semiconductor) transistors and that features stable operation and a broad variable frequency range.
2. Description of the Related Art
A VCO is a crucial circuit for determining the characteristics of a PLL (Phase-Locked Loop). A desirable VCO offers continuous frequency change over a broad frequency band, realizes stable oscillation, and has low noise characteristics.
A ring VCO is typically used in cases in which a VCO is to be integrated in LSI (Large-Scale Integration) such as in an ASIC (Application-Specific Integrated Circuits), because this VCO can be constructed without using inductors or capacitors, and further, the VCO allows the use of differential circuits, which are not vulnerable to noise from the power supply. A circuit described in the paper xe2x80x9cAn Integrable 1-2.5 Gbps Low-Jitter CMOS Transceiver with Built-In Self-Test Capabilityxe2x80x9d (1999 Symposium on VLSI Circuits Digest of Technical Papers 5-2) is typically used as the differential circuit that is used in this type of ring VCO.
Referring now to FIG. 1, a block diagram is shown of the overall construction of one example of a ring VCO of the prior art that is made up of a plurality of gate circuits. In this figure, the internal constructions of basic cells 100-1 to 100-N are all identical, and the internal construction of basic cell 100-1 is shown in FIG. 2 as representative of these basic cells 100-1 to 100-N.
The conventional VCO shown in FIG. 1 is made up of N basic cells 100-1 to 100-N (Nxe2x89xa71) connected in a series. Basic cells 100-1 to 100-N are each provided with: two cell input terminals IN1 and IN2; two cell output terminals OUT1 and OUT2 from which signals that have been received via cell input terminals IN1 and IN2 are outputted in non-inverted form; and two control terminals E and F for receiving signals for controlling the currents that flow through each of basic cells 100-1 to 100-N.
Each of basic cells 100-1 to 100-N are connected in an order such that signals outputted from cell output terminals OUT1 and OUT2 of a preceding-stage basic cell are applied to cell input terminals IN1 and IN2, respectively, of the next-stage basic cell. In addition, output terminals OUT1 and OUT2 of last-stage basic cell 100-N are connected to feed back to input terminals IN2 and IN1, respectively, of first-stage basic cell 100-1 such that the logic is inverted, thereby realizing the oscillation operation.
Referring now to FIG. 2, the construction of basic cells 100-1 to 100-N is next explained with basic cell 100-1 as an example.
Basic cell 100-1 is made up of NMOS (n-channel MOS) transistors M101, M102, and M105; and PMOS (p-channel MOS) transistors M103 and M104. NMOS transistor M101 and PMOS transistor M103 form one set and NMOS transistor M102 and PMOS transistor M104 form another set, these sets constituting a differential circuit in which these set make a pair. The drains of PMOS transistors M103 and M104 are connected to power-supply voltage line V1 in common, the gates of these transistors are connected to control terminal F in common, and the sources of these transistors are connected to the drains of NMOS transistors M101 and M102, respectively. NMOS transistors M101 and M102 have their gates connected to cell input terminals IN1 and IN2, respectively, of basic cell 100-1, and their sources connected to the drain of NMOS transistor M105 in common. In addition, NMOS transistor M105 has its gate connected to control terminal E of basic cell 100-1, and its source connected to power supply voltage V2. The logic of output terminals OUT1 and OUT2 is thus inverted with each other to become the differential output.
Next, regarding the operation of the ring VCO that is constructed according to the foregoing explanation.
In basic cell 100-1, the differential signals that are applied to cell input terminals IN1 and IN2 are outputted as non-inverted signals from cell output terminals OUT1 and OUT2 with a prescribed delay time. The signals that are outputted from cell output terminals OUT1 and OUT2 of basic cell 100-1 are applied to cell input terminals IN1 and IN2 of basic cell 100-2, and similarly outputted as non-inverted signals from cell output terminals OUT1 and OUT2 of basic cell 100-2 with a prescribed delay time. Similarly, signals that are outputted from cell output terminals OUT1 and OUT2 of a preceding-stage basic cell are successively applied to cell input terminals IN1 and IN2 of the next-stage basic cell up to last-stage basic cell 100-N.
The signals that are outputted from cell output terminals OUT1 and OUT2 of last-stage basic cell 100-N are applied to cell input terminals IN2 and IN1, respectively, of first-stage basic cell 100-1 such that the logic of the signals is reversed, i.e., such that the differential logic value are inverted. The oscillation operation is thus obtained by successively applying differential signals that are inputted to basic cell 100-1 to basic cells 100-2 through 100-N, and then applying the differential signals that are outputted from basic cell 100-N to basic cell 100-1.
In this case, the oscillation frequency of the ring VCO is determined by the sum delay time of the number of connected stages of basic cells, with the delay time in each basic cell as a standard.
Furthermore, the current flowing to NMOS transistor M105 is determined by the internal resistances of PMOS transistors M103 and M104 that are regulated based on signals applied to control terminal F, and by signals applied to control terminal E. The delay in each basic cell is determined by the current that flows through this NMOS transistor M105. A desired oscillation frequency can therefore be obtained by using a PLL to control the voltage applied to control terminal E.
Nevertheless, the ring VCO according to the above description has the following problems:
(1) In order to vary the delay time in a basic cell, the internal resistance of PMOS transistors is regulated by means of the control voltage applied to the gate of the PMOS transistors or the current flowing to the basic cells is regulated by means of the control voltage applied to the gates of the NMOS transistors; but since the output amplitude also fluctuates in accordance with this current, there is a possibility danger that the oscillation will be halted depending on the combination of the operating current and the control voltage applied to the PMOS transistors.
(2) Both fluctuation in the power supply voltage and the noise that is generated from the circuit for outputting control signals for regulating the load resistance may cause the voltage across the gate and source of the PMOS transistors for adjusting load to fluctuate, and this tends to cause jitter.
(3) Regarding the characteristics of PMOS transistors, discrepancies that tend to occur in the fabrication process may give rise to variation in the internal resistance that corresponds to the control voltage that is applied to the PMOS transistors. Variation therefore occurs in the load resistance of the basic cells, and this variation complicates the accurate adjustment of delay time in the basic cells.
The present invention was realized in view of the problems of the prior art described hereinabove, and has as an object the provision of a voltage controlled oscillator (VCO) that is capable of a uniform output amplitude, that has minimal jitter, and that has a stable and broad variable frequency range.
The object of the present invention is achieved by a voltage-controlled oscillator that comprises:
a plurality of basic cells; and
a center frequency adjustment circuit that outputs a control signal for setting a delay time for each of the plurality of basic cells;
each of the basic cells comprising:
first and second cell input terminals;
first and second cell output terminals from which signals that have been received from the first and second cell input terminals are outputted in non-inverted form;
a first delay circuit for delaying signals received from the first and second cell input terminals by a delay time that is set based on the control signal outputted from the center frequency adjustment circuit;
a second delay circuit for delaying output signals of the first delay circuit by a delay time that is set independently of the first delay circuit based on the control signal outputted from the center frequency adjustment circuit; and
an adder circuit that adds output signals of the first delay circuit and output signals from the second delay circuit at a proportion that is based on an addition proportion coefficient that is controlled from the outside, and outputs the result of addition;
wherein, in each of the basic cells, the result of addition is applied to the first and second cell output terminals; and
the basic cells are connected in a series such that the first and second cell output terminals of a preceding-stage basic cell are connected to the first and second cell input terminals, respectively, of the next-stage basic cell, and the first and second cell output terminals of the last-stage basic cell are connected to the second and first cell input terminals, respectively, of the first-stage basic cell such that the logic is reversed.
In this case, signals that are applied to the first and second cell input terminals are preferably differential logic signals.
According to the present invention, the oscillation frequency is determined by the delay time of each of the plurality of basic cells and the number of connected stages of basic cells, and the delay time in each of the basic cell is determined by the delay times of each of the first and second delay circuits that make up the basic cell and the addition proportion coefficient for determining the addition proportions of the outputs of these first and second delay circuits. Here, the delay times in each of the first and second delay circuits are preferably determined by the ratio of the values of the currents that flow in the two differential circuits within the delay circuits that are controlled by control signals outputted from the center frequency adjustment circuit, and the value of the addition proportion coefficient are preferably controlled from the outside. In this way, the delay time in each basic cell is the value obtained by adding the value of the delay time in the first delay circuit to the product of the value of the delay time in the second delay circuit and the addition proportion coefficient.
The delay time of each basic cell is shortest and the oscillation frequency is highest when the value of the addition proportion coefficient is 0 because the delay time of each basic cell depends only on the delay time in the first delay circuit. As the value of the addition proportion coefficient increases, the sum of the delay time in the first delay circuit and the delay time in the second delay circuit, which is the delay time in each basic cell, becomes larger; whereby the delay time of each basic cell becomes longer and the oscillation frequency becomes lower.
As can be understood from the foregoing explanation, the variable frequency range of the ring VCO of this invention is determined by the setting of the delay time in the second delay circuit. According to the present invention, the delay times of the basic cells can be set to change stably and continuously over a broad range.
In a case in which each delay circuit is constructed so as to include two differential circuits, adjustment is realized by control signals that are outputted from the center frequency adjustment circuit such that the sum of the values of the currents that flow in the two differential circuits in each of the first and second delay circuits is always uniform, and as a result, the output amplitude of each delay circuit is uniform despite variation of the delay time in each delay circuit, and the output of the basic cells is also stable. In addition, each of the control signals that are applied to the first and second delay circuits and the adder circuit undergoes differential amplification, thereby enabling a reduction of the influence of in-phase noise. Furthermore, the load resistance in each of the differential circuits is the internal resistance of the MOS transistor, but rather than a method of controlling the internal resistance of the MOS transistors by means of a circuit that adjusts the internal resistance, it is possible to use an element that exhibits little fluctuation in resistance due to fluctuation in the power supply voltage and noise from outside circuits. In a case in which such an element is used, noise generated within the load resistance can be greatly reduced, and the influence of fluctuation in the power supply voltage or noise can be greatly reduced compared to the prior art. Moreover, little fluctuation occurs in delay time and an output signal having a low level of jitter can be obtained.
In addition, in a case in which the control signals used for adjusting delay time and the control signals used for adjusting the addition proportion coefficient are differential voltages, the influence of noise can be greatly reduced over the prior art as described hereinabove.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention.